So last Tuesday I was trying to design this buck converter circuit – you know, the usual stuff, picking MOSFETs and all. Kept running into the same headache: every time my simulation looked good, the actual hardware would blow the MOSFET on turn-off. Burnt two FETs on my breadboard, smelled terrible, really frustrating.
After scratching my head for hours, I remembered reading something about this “Miller capacitance” thing affecting turn-off. Honestly, it always sounded super abstract. Digging into the MOSFET datasheet, sure enough, under Gate Charge specs, there’s this Qgd figure staring back at me. That’s the Miller charge they’re talking about.
My Initial Mistake
My first thought? Simple math. I saw Qg (Total Gate Charge) on the datasheet too. Figured the turn-on delay time was just Qg divided by my gate drive current. Set my driver to push 0.5A, did the calculation, felt confident. Plopped down for a coffee.
Watched it on the scope later… disaster. Turn-off lag was huge. The power dissipation? Off the charts. Smoke signals again. That simple calculation totally ignored the weird way the Miller charge locks the gate voltage during that critical turn-off plateau.
Time for a Deep Dive (and Oscilloscope Fun)
Alright, needed better methods. Grabbed the datasheet again. Focused specifically on Qgd. Also looked up the recommended gate driver IC voltage and my actual gate drive resistance.
Here’s the new approach that actually worked:
- Measured the real gate drive voltage swing. Hooked the scope probe directly to the gate and source pins. My driver was pushing from 0V to 10V.
- Found my gate resistor value. Used the tiny resistor between my driver chip and the MOSFET gate – it was 4.7 Ohms. This limits the current surge into the gate.
- Recorded the Qgd value. For my MOSFET, STB42N60M5, Qgd was around 55nC.
The Right Calculations
Now, here’s the good stuff. For the turn-off plateau time (where Miller capacitance bites you):
- Calculate plateau time (t_plateau) = Qgd ÷ (Drive Current)
- Drive Current ≈ Gate Drive Voltage / Gate Resistor! (Approximately, ignoring some chip specifics).
So plugging in my numbers:
- Drive Voltage = 10V (Vdrive)
- Gate Resistor (Rg) = 4.7 Ohms
- Drive Current (I_drive) ≈ Vdrive / Rg = 10V / 4.7 Ω ≈ 2.13A
The calculation gets a bit complex for turn-on/off because different currents flow, but here’s a simple rule of thumb:
- Plateau time ≈ Qgd / I_drive
For the plateau time on turn-off, current flow is less straightforward. Generally, the gate-to-source capacitance discharges through the driver while Miller current flows through the gate-drain capacitance. But as a simplification:
- Approximate plateau time ≈ Qgd / I_drive (same as turn-on)
So, my plateau time became:
- t_plateau ≈ 55nC / 2.13A ≈ 26 nanoseconds.
Checked the scope shot after building the circuit – bam! Turn-off plateau was right around 28ns. Close enough for government work! Power dissipation finally came down from scary levels. The magic was focusing on that Qgd specifically and understanding how the gate resistor directly limits the charge/discharge rate.
Lesson learned big time: ignoring Miller capacitance just kills FETs. Total gate charge (Qg) is important for total energy, but that Qgd? That’s the secret sauce for switching speed and surviving turn-off. Next time, it’s Qgd front and center.